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<title>MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values </title></head>
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<h1>MOVDQA,VMOVDQA32/64—Move Aligned Packed Integer Values</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 6F /r MOVDQA xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move aligned packed integer values from xmm2/mem to xmm1.</td></tr>
<tr>
<td>66 0F 7F /r MOVDQA xmm2/m128, xmm1</td>
<td>MR</td>
<td>V/V</td>
<td>SSE2</td>
<td>Move aligned packed integer values from xmm1 to xmm2/mem.</td></tr>
<tr>
<td>VEX.128.66.0F.WIG 6F /r VMOVDQA xmm1, xmm2/m128</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Move aligned packed integer values from xmm2/mem to xmm1.</td></tr>
<tr>
<td>VEX.128.66.0F.WIG 7F /r VMOVDQA xmm2/m128, xmm1</td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Move aligned packed integer values from xmm1 to xmm2/mem.</td></tr>
<tr>
<td>VEX.256.66.0F.WIG 6F /r VMOVDQA ymm1, ymm2/m256</td>
<td>RM</td>
<td>V/V</td>
<td>AVX</td>
<td>Move aligned packed integer values from ymm2/mem to ymm1.</td></tr>
<tr>
<td>VEX.256.66.0F.WIG 7F /r VMOVDQA ymm2/m256, ymm1</td>
<td>MR</td>
<td>V/V</td>
<td>AVX</td>
<td>Move aligned packed integer values from ymm1 to ymm2/mem.</td></tr>
<tr>
<td>EVEX.128.66.0F.W0 6F /r VMOVDQA32 xmm1 {k1}{z}, xmm2/m128</td>
<td>FVM-RM</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned packed doubleword integer values from xmm2/m128 to xmm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F.W0 6F /r VMOVDQA32 ymm1 {k1}{z}, ymm2/m256</td>
<td>FVM-RM</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned packed doubleword integer values from ymm2/m256 to ymm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F.W0 6F /r VMOVDQA32 zmm1 {k1}{z}, zmm2/m512</td>
<td>FVM-RM</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move aligned packed doubleword integer values from zmm2/m512 to zmm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.128.66.0F.W0 7F /r VMOVDQA32 xmm2/m128 {k1}{z}, xmm1</td>
<td>FVM-MR</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned packed doubleword integer values from xmm1 to xmm2/m128 using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F.W0 7F /r VMOVDQA32 ymm2/m256 {k1}{z}, ymm1</td>
<td>FVM-MR</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned packed doubleword integer values from ymm1 to ymm2/m256 using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F.W0 7F /r VMOVDQA32 zmm2/m512 {k1}{z}, zmm1</td>
<td>FVM-MR</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move aligned packed doubleword integer values from zmm1 to zmm2/m512 using writemask k1.</td></tr>
<tr>
<td>EVEX.128.66.0F.W1 6F /r VMOVDQA64 xmm1 {k1}{z}, xmm2/m128</td>
<td>FVM-RM</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned quadword integer values from xmm2/m128 to xmm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F.W1 6F /r VMOVDQA64 ymm1 {k1}{z}, ymm2/m256</td>
<td>FVM-RM</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned quadword integer values from ymm2/m256 to ymm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F.W1 6F /r VMOVDQA64 zmm1 {k1}{z}, zmm2/m512</td>
<td>FVM-RM</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move aligned packed quadword integer values from zmm2/m512 to zmm1 using writemask k1.</td></tr>
<tr>
<td>EVEX.128.66.0F.W1 7F /r VMOVDQA64 xmm2/m128 {k1}{z}, xmm1</td>
<td>FVM-MR</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned packed quadword integer values from xmm1 to xmm2/m128 using writemask k1.</td></tr>
<tr>
<td>EVEX.256.66.0F.W1 7F /r VMOVDQA64 ymm2/m256 {k1}{z}, ymm1</td>
<td>FVM-MR</td>
<td>V/V</td>
<td>AVX512VL AVX512F</td>
<td>Move aligned packed quadword integer values from ymm1 to ymm2/m256 using writemask k1.</td></tr>
<tr>
<td>EVEX.512.66.0F.W1 7F /r VMOVDQA64 zmm2/m512 {k1}{z}, zmm1</td>
<td>FVM-MR</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Move aligned packed quadword integer values from zmm1 to zmm2/m512 using writemask k1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>FVM-RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>FVM-MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.</p>
<p>EVEX encoded versions:</p>
<p>Moves 128, 256 or 512 bits of packed doubleword/quadword integer values from the source operand (the second operand) to the destination operand (the first operand). This instruction can be used to load a vector register from an int32/int64 memory location, to store the contents of a vector register into an int32/int64 memory location, or to move data between two ZMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a 16 (EVEX.128)/32(EVEX.256)/64(EVEX.512)-byte boundary or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory locations, use the VMOVDQU instruction.</p>
<p>The destination operand is updated at 32-bit (VMOVDQA32) or 64-bit (VMOVDQA64) granularity according to the writemask.</p>
<p>VEX.256 encoded version:</p>
<p>Moves 256 bits of packed integer values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers.</p>
<p>When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte boundary or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory locations, use the VMOVDQU instruction. Bits (MAX_VL-1:256) of the destination register are zeroed.</p>
<p>128-bit versions:</p>
<p>Moves 128 bits of packed integer values from the source operand (second operand) to the destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.</p>
<p>When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory locations, use the VMOVDQU instruction.</p>
<p>128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain unchanged.</p>
<p>VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.</p>
<p><strong>Operation</strong></p>
<p><strong>VMOVDQA32 (EVEX encoded versions, register-copy form)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+31:i] (cid:197) SRC[i+31:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE  DEST[i+31:i] (cid:197) 0</p>
<p>; zeroing-masking</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VMOVDQA32 (EVEX encoded versions, store-form)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+31:i](cid:197) SRC[i+31:i]</p>
<p>ELSE *DEST[i+31:i] remains unchanged*</p>
<p>; merging-masking</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p><strong>VMOVDQA32 (EVEX encoded versions, load-form)</strong></p>
<p>(KL, VL) = (4, 128), (8, 256), (16, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 32</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+31:i] (cid:197) SRC[i+31:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+31:i] remains unchanged*</p>
<p>ELSE  DEST[i+31:i] (cid:197) 0</p>
<p>; zeroing-masking</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VMOVDQA64 (EVEX encoded versions, register-copy form)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197) SRC[i+63:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE  DEST[i+63:i] (cid:197) 0</p>
<p>; zeroing-masking</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VMOVDQA64 (EVEX encoded versions, store-form)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i](cid:197) SRC[i+63:i]</p>
<p>ELSE *DEST[i+63:i] remains unchanged*</p>
<p>; merging-masking</p>
<p>FI;</p>
<p>ENDFOR;</p>
<p><strong>VMOVDQA64 (EVEX encoded versions, load-form)</strong></p>
<p>(KL, VL) = (2, 128), (4, 256), (8, 512)</p>
<p>FOR j (cid:197) 0 TO KL-1</p>
<p>i (cid:197) j * 64</p>
<p>IF k1[j] OR *no writemask*</p>
<p>THEN DEST[i+63:i] (cid:197) SRC[i+63:i]</p>
<p>ELSE</p>
<p>IF *merging-masking*</p>
<p>; merging-masking</p>
<p>THEN *DEST[i+63:i] remains unchanged*</p>
<p>ELSE  DEST[i+63:i] (cid:197) 0</p>
<p>; zeroing-masking</p>
<p>FI</p>
<p>FI;</p>
<p>ENDFOR</p>
<p>DEST[MAX_VL-1:VL] (cid:197) 0</p>
<p><strong>VMOVDQA (VEX.256 encoded version, load - and register copy)</strong></p>
<p>DEST[255:0] (cid:197) SRC[255:0]</p>
<p>DEST[MAX_VL-1:256] (cid:197) 0</p>
<p><strong>VMOVDQA (VEX.256 encoded version, store-form)</strong></p>
<p>DEST[255:0] (cid:197) SRC[255:0] VMOVDQA (VEX.128 encoded version)</p>
<p>DEST[127:0] (cid:197) SRC[127:0]</p>
<p>DEST[MAX_VL-1:128] (cid:197) 0</p>
<p><strong>VMOVDQA (128-bit load- and register-copy- form Legacy SSE version)</strong></p>
<p>DEST[127:0] (cid:197) SRC[127:0]</p>
<p>DEST[MAX_VL-1:128] (Unmodified)</p>
<p><strong>(V)MOVDQA (128-bit store-form version)</strong></p>
<p>DEST[127:0] (cid:197) SRC[127:0]</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VMOVDQA32 __m512i _mm512_load_epi32( void * sa);</p>
<p>VMOVDQA32 __m512i _mm512_mask_load_epi32(__m512i s, __mmask16 k, void * sa);</p>
<p>VMOVDQA32 __m512i _mm512_maskz_load_epi32( __mmask16 k, void * sa);</p>
<p>VMOVDQA32 void _mm512_store_epi32(void * d, __m512i a);</p>
<p>VMOVDQA32 void _mm512_mask_store_epi32(void * d, __mmask16 k, __m512i a);</p>
<p>VMOVDQA32 __m256i _mm256_mask_load_epi32(__m256i s, __mmask8 k, void * sa);</p>
<p>VMOVDQA32 __m256i _mm256_maskz_load_epi32( __mmask8 k, void * sa);</p>
<p>VMOVDQA32 void _mm256_store_epi32(void * d, __m256i a);</p>
<p>VMOVDQA32 void _mm256_mask_store_epi32(void * d, __mmask8 k, __m256i a);</p>
<p>VMOVDQA32 __m128i _mm_mask_load_epi32(__m128i s, __mmask8 k, void * sa);</p>
<p>VMOVDQA32 __m128i _mm_maskz_load_epi32( __mmask8 k, void * sa);</p>
<p>VMOVDQA32 void _mm_store_epi32(void * d, __m128i a);</p>
<p>VMOVDQA32 void _mm_mask_store_epi32(void * d, __mmask8 k, __m128i a);</p>
<p>VMOVDQA64 __m512i _mm512_load_epi64( void * sa);</p>
<p>VMOVDQA64 __m512i _mm512_mask_load_epi64(__m512i s, __mmask8 k, void * sa);</p>
<p>VMOVDQA64 __m512i _mm512_maskz_load_epi64( __mmask8 k, void * sa);</p>
<p>VMOVDQA64 void _mm512_store_epi64(void * d, __m512i a);</p>
<p>VMOVDQA64 void _mm512_mask_store_epi64(void * d, __mmask8 k, __m512i a);</p>
<p>VMOVDQA64 __m256i _mm256_mask_load_epi64(__m256i s, __mmask8 k, void * sa);</p>
<p>VMOVDQA64 __m256i _mm256_maskz_load_epi64( __mmask8 k, void * sa);</p>
<p>VMOVDQA64 void _mm256_store_epi64(void * d, __m256i a);</p>
<p>VMOVDQA64 void _mm256_mask_store_epi64(void * d, __mmask8 k, __m256i a);</p>
<p>VMOVDQA64 __m128i _mm_mask_load_epi64(__m128i s, __mmask8 k, void * sa);</p>
<p>VMOVDQA64 __m128i _mm_maskz_load_epi64( __mmask8 k, void * sa);</p>
<p>VMOVDQA64 void _mm_store_epi64(void * d, __m128i a);</p>
<p>VMOVDQA64 void _mm_mask_store_epi64(void * d, __mmask8 k, __m128i a);</p>
<p>MOVDQA void __m256i _mm256_load_si256 (__m256i * p);</p>
<p>MOVDQA _mm256_store_si256(_m256i *p, __m256i a);</p>
<p>MOVDQA __m128i _mm_load_si128 (__m128i * p);</p>
<p>MOVDQA void _mm_store_si128(__m128i *p, __m128i a);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>None</p>
<p><strong>Other Exceptions</strong></p>
<p>Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;</p>
<table>
<tr>
<td>EVEX-encoded instruction, see Exceptions Type E1.</td></tr>
<tr>
<td>If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.</td></tr></table></body></html>